The present invention relates to LSI (large scale integrated circuit) apparatus, and more particularly relates to so-called multifunctional type LSI apparatus in which an LSI external terminal is shared by a plurality of different functional blocks.
First among the prior-art techniques for controlling a multifunctional type LSI apparatus having a plurality of different functional blocks sharing an LSI external terminal is a technique as disclosed in Japanese Patent Application Laid-Open Hei-8-204128 in which a multiplexer for switching from one functional block to another is mounted so that control is effected with using a selecting signal of the multiplexer as an input signal.
Secondly, there is a technique for switching LSI external terminal as a unit based on a software. An example of this is a commercially available CPU (central processing unit) chip. Such CPU chip is provided with functional blocks such as DMA controller, interrupt controller, memory controller, and timer that are connected to a periphery of CPU module within the chip, and each functional block shares an LSI external terminal in the construction as shown in FIG. 1. This CPU chip is also provided with a functional block called GPIO (General Purpose Input Output) for each LSI external terminal. The function of this functional block is an IO port function through which CPU can monitor input signal values of LSI external terminal (input/output terminal in this case), determine the values to be outputted as output signal, and effect the involved switching of input/output direction.
A description will now be given with respect to the construction and control technique of the prior-art multifunctional type LSI apparatus shown in FIG. 1. The switching between the terminals of functional blocks 1, 2, . . . N, terminal of IO port 106, and a bilateral buffer 103 of an LSI external terminal 120 connected to the external equipments, is effected as follows. In particular, the switching of the input direction is effected by an input switching selector 107, the output direction by an output switching selector 108, and the switching of enabling signal of input/output is effected by an enable switching selector 109. The output switching selector 108 and enable switching selector 109 each are a selector for effecting a simple switching connection. The circuit construction of the input switching selector 107, on the other hand, is to connect the input direction of the bilateral buffer 103 of LSI external terminal 120 to the terminal of one block selected from the functional blocks or IO port 106 and to fix other blocks to non-active level.
The switching enabling signals of each switching selector 107, 108 and 109 are generated at a switch controller 105. The switch controller 105 is provided with a register group at the interior of the controller, which are readable/writable by CPU 101, and it transmits switching enable signals to each switching selector 107, 108 and 109 based on the register value of such register. In such technique, for example as shown in FIG. 2, the connection of the external terminal 120 is switched to IO port when CPU 101 writes “0” to register of the switch controller 105. It is switched to functional block 1 when “1” is written and is switched to functional block N when “N” is written. It should be noted that numeral 102 in FIG. 1 denotes a switching device for switching the connection between the LSI external terminal 120 and the terminals of functional blocks 1, 2, . . . N. It includes: the above described input switching selector 107; output switching selector 108; enable switching selector 109; and an LSI external terminal control block 104 consisting of the IO port 106 and switch controller 105.